1. Field of the Invention
The present invention relates to a first-in-first-out circuit (referred to as FIFO circuit hereinafter), and more particularly to an asynchronous FIFO circuit or the like that ensures reliable data write and data read without using a clock signal.
2. Description of the Related Art
A conventional asynchronous FIFO circuit is known in which data is written and read reliably on different clock signals respectively or without using any clock signal. For example, Japanese Patent Application No. Hei 11-360248 discloses a conventional asynchronous FIFO circuit.
On the other hand, PC16550D manufactured by National Semiconductor Co. of U.S.A. is an industry-standard format of a start-stop synchronous serial communication device, and incorporates two 16-word asynchronous FIFO circuits for transmitting and receiving data.
As shown in FIG. 9, the asynchronous FIFO circuit (referred to receiver FIFO hereinafter) of PC16550D for receiving data stores words in sequence therein, each of the words including 8-bit data and 2-bit error flags. The major feature of PC16550D is that the Bit of the Line Status Register(referred to as LSR7 hereafter) can be read out as an indication as to whether at least one error flag is set to 1 in the receiver FIFO circuit.
The error flags are written into and read from the receiver FIFO circuit together with received data. Accordingly, the LSR7 bit changes in state when the received data is written into and read from the receiver FIFO circuit.
The LSR 7, as shown in FIG. 10, is a logical sum of all the columns that correspond to the error flags of respective words stored in the receiver FIFO. For PC16550, the LSR 7 is a logical sum of all the error flags of a total of 16 words.
If the number of words of the receiver FIFO circuit is increased, a serious inconvenience is encountered in configuring the receiver FIFO circuit. This is because a general purpose memory macro cannot be used to configure a receiver FIFO circuit.
In other words, increasing the number of words in the receiver FIFO circuit increases the number of columns that are involved in the generation of LSR 7 because the 7-bit LSR is a logical sum of all the columns that correspond to error flags of the respective words. When the number of words is increased, output lines must be needed to read independently from columns corresponding to the error flags of words stored in the memory that forms the receiver FIFO circuit. Therefore, a general-purpose memory macro cannot be used in order to increase the number of words. Increasing the number of words will increase chip area or the number of gates required.
This type of inconvenience becomes more prominent when a start-stop synchronous serial communication device is to be implemented by using ASIC (Application Specific Integrated Circuit) technique.
For example, Oxford Semiconductor Co. of U.K. sells OX16C950 that features compatibility with PC16550D, OX16C950 incorporating a 128-word asynchronous FIFO circuit for receiving and transmitting data. OX16C950 has a PC16550D-compatible feature and the number of words for a FIFO circuit extended to 128 words for both receiver and transmitter.
However, OX16C950 does not provide an LSR 7 that is a logical sum of all the error flags stored in the receiver FIFO circuit. Instead, when a receiving error occurs, OX16C950 is set and merely cleared immediately after 7-bit LSR is read out. Therefore, even if an error flag set to 1 exists in the receiver FIFO immediately after the 7-bit LSR has been read out, the 7-bit LSR is cleared. In this case, OX16C950 loses its compatibility with PC16550D.
This fact indicates that the software developed for PC16550D does not always run properly with OX16C950, impairing the commercial acceptance of OX16950.
The present invention was made in view of the aforementioned drawbacks. An object of the invention is to permit a FIFO circuit to be configured by using a general-purpose memory macro, the FIFO circuit being such that a LSR 7 is read to determine whether at least one word having a bit of a particular column set to 1 exists. The FIFO according to the present invention operates just like a receiver FIFO circuit incorporated in a conventional start-stop synchronous serial communication device compatible with PC16550D, which is an industry-standard format of start-stop synchronous serial communication device.
One aspect of the present invention is an asynchronous FIFO circuit comprising:
a memory;
asynchronous reading and writing means of reading a predetermined amount of data from and of writing the predetermined amount of data into said memory on a first-in-first-out basis;
an error write counter of counting counts up by 1 if the predetermined amount of data written into said memory contains an error;
an error read counter of counting up by 1 if the predetermined amount of data read from said memory contains an error;
comparing means of comparing a value of said error write counter with a value of said error read counter, said comparing means outputting a logic level of 0 when the value of said error write counter is coincident with the value of said error read counter, said comparing means outputting a logic level of 1 if the former value is different from the latter value.
Another aspect of the present invention is an asynchronous FIFO circuit comprising:
a memory having addresses for 2N words, N being an integer;
a write pointer of counting up by 1 when writing of data into said memory has been completed, said write pointer counting up by 1 if the memory is not in a full state where the memory is full of data;
a read pointer of counting up by 1 when reading of data from said memory has been completed, said read pointer counting up by 1 if the memory is not in an empty state where all data has been read from said memory;
a previous read pointer of outputting an output incremented by 1 when reading of data has been completed, said previous read pointer outputting an output incremented by 1 if said memory is not in the empty state, said previous read pointer always outputting the output one less value than the value of said read pointer;
an empty flag generating circuit of detecting the empty state when a value of said write pointer is coincident with a value of said read pointer;
a full flag generating circuit of detecting the empty state of said memory when the value of said write pointer is coincident with a value of said previous read pointer;
a write pointer decoder of decoding the value of said write pointer to generate an address at which data is allowed to be written into said memory;
a data selector of selecting data from an address obtained by decoding the value of said read pointer;
a write flag OR circuit of taking a logic sum of predetermined bits contained in data written into said memory;
a read flag OR circuit of taking a logic sum of predetermined bits contained in data read from said memory;
an error write counter of counting up by 1 if said write flag OR circuit outputs a true logic level when data is written into said memory;
an error read counter of counting up by 1 if said read flag OR circuit outputs a true logic level when data is read from said memory; and
an error comparing circuit of comparing a value of said error write counter with a value of said error read counter to detect whether the value of said error write counter and the value of said error read counter coincide.
Still another aspect of the present invention is the asynchronous FIFO circuit wherein said error write counter and said error read counter are formed of a gray code counter.
Yet still another aspect of the present invention is an asynchronous FIFO data reading and writing method comprising:
an asynchronous reading and writing step of reading a predetermined amount of data from and writing the predetermined amount of data into a memory on a first-in-first-out basis;
an error write counting step of counting up by 1 if the predetermined amount of data written into said memory contains an error;
an error read counting step of counting up by 1 if the predetermined amount of data read from said memory contains an error;
a comparing step of comparing a value of said error write counting step with a value of said error read counting step, said comparing step outputting a logic level of 0 when the value of said error write counting step is coincident with the value of said error read counting step, said comparing step outputting a logic level of 1 if the former value is different from the latter value.
Still yet another aspect of the present invention is an asynchronous FIFO data reading and writing method comprising:
a write point step of counting up by 1 when writing of data into a memory has been completed, said memory having addresses for 2N words, N being an integer, said write point step counting up by 1 if the memory is not in a full state where the memory is full of data;
a read point step of counting up by 1 when reading of data from said memory has been completed, said read point step counting up by 1 if the memory is not in an empty state where all data has been read from said memory;
a previous read point step of outputting an output incremented by 1 when reading of data from said memory has been completed, said previous read point step outputting an output incremented by 1 if said memory is not in the empty state, said previous read point step always outputting the output one less value than said read pointer;
an empty flag generating step of detecting the empty state when a value of said write pointer is coincident with a value of said read point step;
a full flag generating step of detecting the full state of said memory when the value of said write pointing step is coincident with a value of said previous read pointing step;
a write pointer decode step of decoding the value of said write pointing step to generate an address at which data is allowed to be written into said memory;
a data select step of selecting data from an address obtained by decoding the value of said read pointing step;
a write flag OR step of taking a logic sum of predetermined bits contained in data written into said memory;
a read flag OR step of taking a logic sum of predetermined bits contained in data read from said memory;
an error write count step of counting up by 1 if said write flag OR step outputs a true logic level when data is written into said memory;
an error read count step of counting up by 1 if said read flag OR step outputs a true logic level when data is read from said memory; and
an error comparing step of comparing a value of said error write count step with a value of said error read count step to detect whether the value of said error write count step and the value of said error read count step coincide.
A further aspect of the present invention is the asynchronous FIFO data reading and writing method wherein said error read write step an said error read step are formed of a gray code count step.
The aforementioned present invention is advantageous in that configuring a memory by the use of a general-purpose memory macro also ensures reading information as to whether at least one error flag set to 1 exists in the FIFO circuit.
The present invention is also advantageous in that no glitch occurs in a detection output that indicates whether at least one error flag set to 1 exists in the FIFO circuit.